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dc.contributor.advisorBehjat, Laleh
dc.contributor.advisorRakai, Logan M.
dc.contributor.authorFarshidi, Ali
dc.date2019-11
dc.date.accessioned2019-08-12T17:05:09Z
dc.date.available2019-08-12T17:05:09Z
dc.date.issued2019-08-09
dc.identifier.citationFarshidi, A. (2019). Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing (Unpublished master's thesis). University of Calgary, Calgary, AB.en_US
dc.identifier.urihttp://hdl.handle.net/1880/110709
dc.description.abstractClock network synthesis is an important stage of the Integrated Circuit (IC) design cycle. The performance of the IC highly depends on the clock network synthesis which makes this stage critical where accuracy is very important. In this thesis, a new delay model is proposed for clock networks that is capable of estimating clock signal delay with significantly improved accuracy in a relatively low runtime. This model is developed using Least square fitting by employing data oriented training. The developed model is formulated in the form of posynomials which makes it a suitable option for application in geometric programming gate and clock network sizing optimization frameworks. The experimental results demonstrate the effectiveness of the proposed delay model in predicting the delay at the timing critical clock sinks in the clock network, i.e. sinks with minimum and maximum delays, and the estimated values are, on average, 20 ps closer than the Elmore values to the reference circuit simulator tool, ngspice. This is while the runtime of the proposed delay model is negligible compared to the ngspice simulations. This helps designers obtain accurate delay estimations in low runtime for quick optimization iterations. In addition, a clock network buffer sizing approach is developed which includes an objective function with geometric programming format considering two competing objectives, power consumption and clock skew. The clock slew and technology constraints are also integrated into this optimization problem. The clock network buffer sizing experiments show significant improvements compared to the initial clock networks in terms of clock skew, up to 183 ps, while the power consumption improves for all test cases, on average by 54%.en_US
dc.language.isoengen_US
dc.rightsUniversity of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.en_US
dc.subjectVery Large Scale Integrationen_US
dc.subjectClock Network Buffer Sizingen_US
dc.subjectVLSIen_US
dc.subjectDelay Modelingen_US
dc.subjectGeometric Programmingen_US
dc.subject.classificationEngineering--Electronics and Electricalen_US
dc.titleDevelopment of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizingen_US
dc.typemaster thesisen_US
dc.publisher.facultySchulich School of Engineeringen_US
dc.publisher.institutionUniversity of Calgaryen
thesis.degree.nameMaster of Science (MSc)en_US
thesis.degree.disciplineEngineering – Electrical & Computeren_US
thesis.degree.grantorUniversity of Calgaryen_US
dc.contributor.committeememberDimitrov, Vassil
dc.contributor.committeememberYanushkevich, Svetlana N.
ucalgary.item.requestcopytrueen_US


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